Description

M34E02-F

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DocID10367 Rev 14

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Description

Memory) organized as 256 × 8 bits.

The M34E02-F can be accessed with a supply voltage from 1.7 V to 5.5 V and operates with

a clock frequency of 400 kHz (or less), over an ambient temperature range of -40 °C /

+85 °C.

Figure 1. Logic diagram

The M34E02-F is able to lock permanently the data in its first half (from location 00h to 7Fh).

This facility has been designed specifically for use in DRAM DIMMs (dual interline memory

modules) with serial presence detect (SPD). All the information concerning the DDR1,

DDR2 or DDR3 configuration of the DRAM module (such as its access speed, size and

organization) can be kept write-protected in the first half of the memory.

The first half of the memory area can be write-protected using two different software write

protection mechanisms. By sending the device a specific sequence, the first 128 bytes of

the memory become write protected: permanently or resettable. In addition, the devices

allow the entire memory area to be write protected, using the WC input (for example by

organized as 256 × 8 bits.

The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the

(0110) to define the protection. These codes are used together with the voltage level applied

on the three chip enable inputs (E2, E1, E0).

synchronized by the serial clock. Read and Write operations are initiated by a Start

condition, generated by the bus master. The Start condition is followed by a device select

code and RW bit (as described in the Device select code table), terminated by an

acknowledge bit.

time, following the bus master’s 8-bit transmission. When data is read by the bus master,

AI09020c

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E0-E2

SDA

VCC

M34E02-F

WC

SCL

VSS