Maximum ratings

STHDLS101T

16/26

5.2

TMDS outputs (OUT_D signals)

The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The

HDMI 1.3 specification is assumed to be the correct reference in instances where this

document conflicts with the HDMI 1.3 specification.

Table 9.

Differential output characteristics for TMDS OUT_D signals

Symbol

Parameter

Comments

Min

Typ

Max

Unit

Single-ended high

level output voltage

voltage in the HDMI or DVI

V

V

Single-ended low level

output voltage

The open-drain output pulls

600 mV

500 mV

400 mV

V

Single-ended output

swing voltage

Swing down from TMDS

termination voltage

(3.3 V ±10%)

400 mV

500 mV

600 mV

V

Single-ended current

in high-Z state

Measured with TMDS outputs

through 50

Ω resistors

10

µA

Rise time

Maximum rise/fall time at

2.7 Gbps = 148ps. 125ps =

148 – 15%

125 ps

0.4 Tbit

ps

Fall time

Maximum rise/fall time at

2.7 Gbps = 148 ps.

125ps = 148 – 15%

125 ps

0.4 Tbit

ps

INTRA

Intra-pair differential

skew

This differential skew budget

is in addition to the skew

presented between D+ and D-

paired input pins.

10

ps

INTER

Inter-pair lane to lane

output skew

This lane to lane skew budget

is in addition to the skew

between differential input

pairs.

250

ps

Jitter added to TMDS

signals

Jitter budget for TMDS

signals as they pass through

the level shifter.

7.4 ps = 0.02 Tbit at 2.7 Gbps

7.4

ps

Obsolete

Product(s)

- Obsolete

Product(s)