STHDLS101T datasheet(18/26 Pages) STMICROELECTRONICS

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STHDLS101T

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5.4

DDC input and output chatacteristics

Table 11.

SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics

Symb

Parameter

Comment

Min

Typ

Max

Unit

Input voltage on SDA_SINK, SCL_SINK pins

Voltage on the DDC pins on

connector end

05.5

ILKG

Input leakage current on SDA_SINK, SCL_SINK

pins

VCC =3.3 V

VI =0.1VDD to 0.9 VDD to

isolated DDC inputs

VDD = external pull-up

resistor voltage on

SDA_SINK and SCL_SINK

inputs (maximum of 5.5 V)

-10

µA

IOFF

Power-down leakage current on SDA_SINK,

SCL_SINK pins

VCC =0.0 V

VI = 0.1 VDD to 0.9 VDD to

DDC sink inputs

VDD = external pull-up

resistor voltage on

SDA_SINK and SCL_SINK

inputs (maximum of 5.5 V)

SDA_SOURCE,

SCL_SOURCE = 0.0 V

-10

µA

CI/O

Input/output capacitance

(switch off)

VI(pp)=1 V, 100 KHz

VCC=3.3 V, T=25C

5pF

CI/O

Input/output capacitance

(switch on)

VI(pp)=1 V, 100KHz

VCC = 3.3 V, T= 25

° C

RON

Switch resistance

IO=3 mA, VO =0.4 V

VCC =3.3 V

TPD

DDC_SINK to DDC_SOURCE propagation delay

Time from DDC_SINK

changing state to

DDC_SOURCE changing

state while the pass gate is

enabled.

CL=10 pF

RPU=1.5 K (min), 2.0 K

(max)

815

TSX

Switch time from DDC_EN to the valid state on

DDC_SOURCE

CL =10 pF

RPU = 1.5 K (min), 2.0 K

(max)

815

Obsolete

Product(s)

- Obsolete

Product(s)

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