STPMS2

Theory of operation

DocID16525 Rev 5

19/36

9

Theory of operation

9.1

General operation description

The STPMS2 performs the second-order analog modulation of two channels in parallel,

with appropriate non-overlapping control signal generator, of signals with frequencies

varying from DC to 4 kHz on two independent channels in parallel. The outputs of the

converters provide two digital streams of ones and zeroes, which can be then multiplexed

to reduce the number of external connections. The STPMS2 converts analog signals on

two independent channels in parallel via delta-

sigma (ΣΔ) analog-to-digital converters into

a binary stream of sigma-delta signals. The device is particularly suitable to measure

electrical line parameters (voltage and current) via analog signals from voltage sensors

(current divider) and current sensors (inductive Rogowski coil, current transformer or shunt

resistors). There is a current channel for line current and a voltage channel for line voltage.

The current channel input is connected through an external anti-aliasing RC filter to a

Rogowski coil, current transformer (CT) or shunt current sensor which converts line current

into an appropriate voltage signal. The current channel includes a low-noise voltage

preamplifier with programmable gain. The voltage channel is connected directly through a

resistor voltage divider and anti-aliasing filter to a line voltage modulator (ADC). Both

channels have quiescent zero signal point at GND, so the STPMS2 is able to sample

differential signals on both channels with their zero point around

GND. The converted ΣΔ

signals are multiplexed so to reduce the number of external connections. The conversion

and the multiplex are driven by external clock signal CLK. The device is used with a digital

signal processing circuit to implement a measuring system of a multi-phase power meter.

The STPMS2 also includes a temperature compensated bandgap reference voltage

generator, low drop supply voltage regulator and minimal digital circuitry that includes BIST

(built-in self-test) structures. In a current signal processing channel, a low-noise

preamplifier is included upstream of the sigma-delta converter. All reference voltages are

designed to eliminate channel crosstalk. The STPMS2 can operate in fast (HP) or low-

power (LP) mode (see also Table 7). In fast mode, a nominal clock frequency of 4.1 or 4.9

MHz is applied to the clock input. In this mode, signal bandwidth is specified between 0 and

4 kHz. In low-power mode, the nominal clock is four times slower (1 MHz) to lower the

power consumption of the circuit. In low-power mode, the quiescent bias currents of the

preamplifier and sigma-delta integrators are reduced and the signal bandwidth is narrowed

to the frequency bandwidth from 0 to 1 kHz. The mode of operation and configuration of the

device can be selected by wiring configuration pins (MS0, MS1, MS2 and MS3) to VCC,

GND, CLK or NCLK signal. This approach can be used to change the settings of a current

channel, sigma-delta stream output mode and temperature compensation curve of an

internal bandgap reference. These pins can act as a serial port to change the configuration

of the device.

9.2

Functional description of the analog part

The supply pins for the analog part are VCC, VDDa, VDDac, VDDav, VBG and GND. The

GND pin also represents a reference point. The VDDa is an analog I/O pin of the internal

+3.0 V low drop voltage regulator and the VDDac and VDDav are the modulator supply

in

puts. A capacitor of 1 μF should be connected between VDDxx and GND. The input of

the regulator is VCC, which also powers the bandgap and bias generators. The bandgap

output pin is VBG, which should be connected to GND via a capacitor of 100 nF.