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L9658 数据表(PDF) 17 Page - STMicroelectronics

部件名 L9658
功能描述  Analog output available for resistance
PDF  64 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L9658 数据表(HTML) 17 Page - STMicroelectronics

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L9658
Electrical specification
Doc ID 14219 Rev 3
17/64
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40° C to +95 °C
All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.
Figure 5.
SPI timing diagram
Figure 6.
SPI timing measurement
Table 11.
SPI timing
No.
Symbol
Parameter
Min
Typ
Max
Unit
-
fop
Transfer frequency
dc
-
5.50
MHz
1tSCK
SCLK, SCLK_A Period
181
-
-
ns
2tLEAD
Enable lead time
65
-
-
ns
3tLAG
Enable lag time
50
-
-
ns
4tSCLKHS
SCLK, SCLK_A high time
65
-
-
ns
5tSCLKLS
SCLK, SCLK_A low time
65
-
-
ns
6tSUS
MOSI, MOSI_A input setup time
20
-
-
ns
7tHS
MOSI, MOSI_A input hold time
20
-
-
ns
8tA
MISO, MISO_A access time
-
-
60
ns
9tDIS
MISO, MISO_A disable time (1)
--
100
ns
10
tVS
MISO, MISO_A output valid time
-
-
66
ns
11
tHO
MISO, MISO_A output hold time (1)
0-
-
ns
12
tRO
Rise Time (Design Information)
-
-
30
ns
13
tFO
Fall Time (Design Information)
-
-
30
ns
14
tCSN
CS_A, CS_D, CS_S negated time
640
-
-
ns
1.
Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on
the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time,
and minimum capacitance on MISO is the worst case for output hold time.
SCLK
DON'T
CARE
MISO
MOSI
CS
t
LAG
t
CSN
f
OP
t
SCLKHS
t
LEAD
t
SCLKLS
t
VS
t
A
t
SUS
t
HS
t
RO, tFO
t
HO
t
DIS
MSB IN
LSB IN
DATA
MSB OUT
LSB OUT
DATA
+5 V
1.0 V
4.0 V
0V
CS
MISO
VDD
MISO
t
DIS
1k
1k



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