12

ATSAM9708

1772D–DRMSD–01/04

.

Notes:

1. When data is already loaded into internal ATSAM9708 output register. In this case PC_READY stays high during the read

cycle.

2. PC_READY goes into low only if the data is not ready to be loaded into/read from internal ATSAM9708 register. 128 t

responds to a single worst-case situation. At f

ISA bus timing.

3. PC_IO16 is asserted low by ATSAM9708 if A2A1 = 10 to indicate fast 16-bit ISA bus transfer to the PC.

Table 10. PC Host Interface Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

t

AVCS

Address valid to chip select low

0

ns

t

CSLDRL

Chip select low to PC_RD low

5

ns

t

RDHCSH

PC_RD high to PC_CS high

5

ns

t

PRD

PC_RD pulse width

50

ns

t

RDLDV

20

ns

t

DRH

Data out hold from PC_RD

510

ns

t

RDLIORL

010

ns

t

PIRO

128

t

ck

t

IORHDV

0ns

t

CSLIOCS

020

ns

t

CSHIOCS

020

ns

t

CSLWRL

PC_CS low to PC_WR low

5

ns

t

WRHCSH

PC_WR high to PC_CS high

5

ns

t

PWR

PC_WR pulse width

50

ns

t

WRLIORL

010

ns

t

IORHWRH

5ns

t

DWS

Write data setup time

10

ns

t

DWH

Write data hold time

0

ns