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ATSAM9708

1772D–DRMSD–01/04

Recommended Board

Layout

Like all HCMOS high-integration ICs, some rules of board layout should be followed for

reliable device operation:

GND, V

Distribution,

Decouplings

All GND, V

mended below the ATSAM9708. The board GND and V

form. If 3.3V is not available, then V

series.

Recommended decoupling is 0.1 µF at each corner of the IC with an additional 10 µF

decoupling close to the crystal. V

Crystal, LFT

The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-

R and the ATSAM9708 should be short and shielded. The ground return from the com-

pensation capacitors and LFT filter should be the GND plane from ATSAM9708.

Buses

Parallel layout from PC_D[15:0] and DRA[11:0]/WD[15:0] should be avoided. The

PC_D[15:0] bus is an asynchronous high-transient current-type bus. Even on short dis-

tances, it can induce pulses on DRA[11:0]/WD[15:0] which can corrupt addresses

and/or data on these buses.

A ground plane should be implemented below the PC_D[15:0] bus, which connects both

to the PC-ISA connector and to the ATSAM9708 GND.

A ground plane should be implemented below the DRA[11:0]/WD[15:0] bus, which con-

nects both to the DRAM SIMM grounds and to the ATSAM9708.

Analog Section

A specific AGND ground plane should be provided, which connects to the GND ground

by a single trace. No digital signals should cross the AGND plane. Refer to the Codec

vendor recommended layout for correct implementation of the analog section.