25

ATSAM9708

1772D–DRMSD–01/04

Bi-processor

Operation

Each PDSP has access to the same memory space. Sample data, buffers and pro-

grams can therefore be shared between the two PDSPs, thus minimizing memory

requirements.

Each P16 has the possibility to test a read-only bit that identifies the PDSP number it

belongs to (PDSPID). This allows the firmware to make decisions according to the pro-

cessor currently executing the code.

As an example, consider implementation of a 128-voice synthesizer. An easy way to

share traffic between the two PDSPs would be to have PDSP#1 process even MIDI-

numbered notes, while the PDSP#2 would process odd MIDI-numbered notes.

In this case, there would only be a single firmware processed by both P16s, with some

coding as follows:

If (PDSPID == 0 && noteeven) then ProcessNote();

If (PDSPID == 1 && noteodd) then ProcessNote();

The two PDSPs may also execute completely different firmware. In this case, as both

types of firmware start from address 100H, a test on PDSPID should be done at the

beginning of the program to jump to the correct firmware.

Reset and Power-

down

During power-up, the RESET input should be held low until the crystal oscillator and

PLL are stabilized. This may take about 20 ms. The RESET signal is normally derived

from the PC master reset. However, a typical RC/diode power-up network can also be

used for some applications.

After the low-to-high transition of RESET, the following occurs:

•If REFRESH is sampled high at the low to high transition of RESET then the

external SDRAM init cycles are executed (see “Memory Type Configuration and

Boot Configuration” on page 26).

•

Both Synthesis/DSP enter an idle state.

•If REFRESH is low, then both P16 program execution starts from address 0100H in

ROM space (WCS0 low).

•If REFRESH is high, then both P16 program execution starts from address 0000H in

internal bootstrap ROM space. Each internal bootstrap expects to receive 256

words from its respective 16-bit burst transfer port, which will be stored from 0100H

GPIO_OUT[7] DSP#2

SD_IN[7]

GPIO_IN[0] DSP#1

SD_IN[0]

GPIO_IN[1] DSP#1

SD_IN[1]

GPIO_IN[2] DSP#1

SD_IN[2]

GPIO_IN[3] DSP#1

SD_IN[3]

GPIO_IN[0] DSP#2

MIDI2_IN

GPIO_IN[1] DSP#2

SD_IN[5]

GPIO_IN[2] DSP#2

SD_IN[6]

GPIO_IN[3] DSP#2

SD_IN[7]

Table 17. General-purpose Input/Output Routing (Continued)

GPIO

Pin