AT89C51AC3-RDTIM datasheet(31/141 Pages) ATMEL

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AT89C51AC3

4383A–8051–10/04

Power Management

Introduction

Two power reduction modes are implemented in the AT89C51AC3. The Idle mode and

the Power-Down mode. These modes are detailed in the following sections. In addition

to these power reduction modes, the clocks of the core and peripherals can be dynami-

cally divided by 2 using the X2 mode detailed in Section “Clock”, page 15.

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

preserved, i.e., the program counter and program status word register retain their data

for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The

status of the Port pins during Idle mode is detailed in Table 9.

Entering Idle Mode

To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51AC3

enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that

sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT89C51AC3 enters Power-Down mode.

Then it does not go in Idle mode when exiting Power-Down mode.

Exiting Idle Mode

There are two ways to exit Idle mode:

Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the AT89C51AC3 and vectors the CPU to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-Down Mode

The Power-Down mode places the AT89C51AC3 in a very low power state. Power-

Down mode stops the oscillator, freezes all clock at known states. The CPU status prior

to entering Power-Down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-Down mode. In addition, the SFR

and RAM contents are preserved. The status of the Port pins during Power-Down mode

is detailed in Table 9.

Note:

VCC may be reduced to as low as V

RET during Power-Down mode to further reduce

power dissipation. Take care, however, that VDD is not reduced until Power-Down mode

is invoked.

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