AT89C51AC3-RDTIM datasheet(42/141 Pages) ATMEL

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AT89C51AC3

4383A–8051–10/04

FM0 Memory Architecture

The Flash memory is made up of 4 blocks (see Figure 23):

•

The memory array (user space) 64K Bytes

•

The Extra Row

•

The Hardware security bits

•

The column latch registers

User Space

This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128

Bytes. It contains the user’s application code.

Extra Row (XRow)

This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor-

mation for boot loader usage.

Hardware security Byte (HSB)

The Hardware security Byte space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software (from FM0 and , the 4 LSB can only be read

by software and written by hardware in parallel mode.

H Hardware Security Byte (HSB)

Column Latches

The column latches, also part of FM0, have a size of full page (128 Bytes).

The column latches are the entrance buffers of the three previous memory locations

(user array, XROW and Hardware security byte). The column latches are write only and

can be accessed only from FM1 (boot mode) and from external memory

Cross Flash Memory Access

Description

The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from

external memory is impossible.

The FM1 memory can be program only by parallel programming.

The Table show all software Flash access allowed.

7654

3210

BLJB

LB2

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

7X2

X2 Mode

Programmed (=’0’) to force X2 mode (6 clocks per instruction) after reset

Unprogrammed to force X1 mode, Standard Mode, afetr reset (Default)

6BLJB

Boot Loader Jump Bit

When unprogrammed (=’1’), at the next reset :

-ENBOOT=0 (see code space memory configuration)

-Start address is 0000h (PC=0000h)

When programmed (=’0’)at the nex reset:

-ENBOOT=1 (see code space memory configuration)

-Start address is F800h (PC=F800h)

Reserved

2-0

LB2-0

General Memory Lock Bits (only programmable by programmer tools)

Section “Flash Protection from Parallel Programming”, page 51

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