CS5529

DS246F1

17

Port Flag

The port flag bit in the configuration register allows

the user to select the mode in which conversions

will be presented to the serial port. With the port

flag bit cleared, the user must read the conversion

data register. With the port flag bit set to logic 1, the

user can read the conversion data from the serial

port by first issuing the NULL command to clear

the SDO flag and then issuing 24 SCLKs to read

the conversion word.

Calibration

Calibration is used to set the zero and gain slope of

the ADC’s transfer function. The calibration con-

trol bits in the configuration register allow the user

to perform either self calibration or system calibra-

tion.

The offset and gain calibration steps each take one

conversion cycle to complete. At the end of the cal-

ibration step, the calibration control bits will be set

back to logic 0, and the DF (Done Flag) bit will be

set to a logic 1. For the combination self-calibration

(CC2-CC0= 011; offset calibration followed by

gain calibration), the calibration will take two con-

version cycles to complete and will set the DF bit

after the gain calibration is completed.

Note:

1) The DF bit will be cleared any time the data

register, the offset register, the gain register,

or the setup register is read. Reading the

configuration register alone will not clear the

DF bit. 2) After the CS5529 is reset, the

converter is functional and can perform

measurements without being calibrated. In

this case, the converter will utilize the

initialized values of the on-chip registers

(Gain = 1.0, Offset = 0.0) to calculate output

words. Any initial offset and gain errors in the

internal circuitry of the chip will remain.

Calibration Registers

The offset calibration result is stored in the offset

register. The result is used during the conversion

process to nullify offset errors. One LSB in the off-

polar span is 2 times the unipolar span). The MSB

in the offset register determines if the offset to be

trimmed is positive or negative (0 positive, 1 nega-

tive). The converter can typically trim ±50 percent

of the input span. Refer to the following Offset

Register and Gain Register descriptions for details.

Offset Register

Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data). After reset, all bits

are ‘0’.

23(MSB)

22

21

20

19

18

1716151413

12

Sign

0

0

0

0

0

0

0

0000

0

11

10

9

8

7

6

5

4321

0

0

0

0

0

0

0

0

0000

0