CS5529-AP datasheet(19/30 Pages) CIRRUS

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CS5529

DS246F1

tions). If a system gain calibration is performed, the

calibrated input must not cause the resulting gain

3.9999998. The above condition requires that the

full scale input voltage to be greater than 25 percent

of the differential reference voltage (i.e. a 625mV

input signal must be applied if the differential ref-

erence voltage is 2.5V).

Limitations in Calibration Range

System calibration can be limited by signal head-

room in the analog signal path inside the chip as

discussed under the Analog Input section of this

data sheet. For gain calibration the full scale input

signal can be reduced to the point in which the gain

or FFFFFF (hexadecimal). Under nominal condi-

tions, this occurs with a full scale input signal equal

to about 1/4 the reference voltage. With the con-

verter’s intrinsic gain error, this full scale input sig-

nal may be higher or lower. In defining the

minimum Full Scale Calibration Range (FSCR)

under “Analog Characteristics”, margin is retained

to accommodate the intrinsic gain error. Alterna-

tively the input full scale signal can be increased to

a point which exceeds the operating range of the

analog circuitry. This occurs when the input volt-

age is approximately 1.5X the differential refer-

ence voltage (Gain Register = 1.0).

Calibration Tips

Calibration steps are performed at the output word

rate selected by the WR2-WR0 bits of the configu-

ration register. Since higher word rates result in

conversion words with more peak-to-peak noise,

calibration should be performed at lower output

word rates. Also, to minimize digital noise near the

device, the user should wait for each calibration

step to be completed before reading or writing to

the serial port.

Factory calibration can be performed in a user’s

system by using the system calibration capabilities

of the CS5529. After the ADC is calibrated in the

user’s system, the offset and gain register contents

can be read by the system microcontroller and re-

corded in EEPROM. These same calibration words

can then be uploaded into the offset and gain regis-

ters of the converter when power is first applied to

the system.

A user can scale the input range by modifying the

gain register. For example, if a self or system cali-

bration is performed with a full scale of 2.5 V and

a full scale of 1.25 V is desired, the user can modify

the gain register to double its slope. This can be

done by reading the gain register, shifting the bina-

ry word one position to the left (this multiplies the

gain word by 2), and writing this word back into the

gain register. The gain register can be scaled by any

amount as long as it does not exceed a decimal

range of 0.25 to 4.0.

One of two methods can be used to determine when

a calibration is complete: 1) if the PF (Port Flag) bit

of the configuration register is set to logic 1, SDO

falls to logic 0 at the completion of a calibration; or

2) regardless of the PF bit, the DF (Done Flag) bit

in the configuration register is set at completion of

calibration. The user can either monitor the DF bit

or SDO to determine when a calibration is com-

plete. Whichever method is used, the calibration

control bits (CC2-CC0) automatically return to log-

ic 0 upon completion of any calibration.

External

Connections

Full Scale

AIN+

AIN-

Figure 9. System Calibration of Gain.

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