数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS5529-AP 数据表(PDF) 18 Page - Cirrus Logic

部件名 CS5529-AP
功能描述  16 BIT PROGRAMMABLE ADC WITH 6 BIT LATCH
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS5529-AP 数据表(HTML) 18 Page - Cirrus Logic

Back Button CS5529-AP Datasheet HTML 14Page - Cirrus Logic CS5529-AP Datasheet HTML 15Page - Cirrus Logic CS5529-AP Datasheet HTML 16Page - Cirrus Logic CS5529-AP Datasheet HTML 17Page - Cirrus Logic CS5529-AP Datasheet HTML 18Page - Cirrus Logic CS5529-AP Datasheet HTML 19Page - Cirrus Logic CS5529-AP Datasheet HTML 20Page - Cirrus Logic CS5529-AP Datasheet HTML 21Page - Cirrus Logic CS5529-AP Datasheet HTML 22Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 30 page
background image
CS5529
18
DS246F1
Gain Register
The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is ‘1’, all other bits are ‘0’.
The gain calibration results is stored in the gain
register. The result sets the slope of the ADC’s
transfer function. The gain register spans from 0 to
(4 - 2-22). The decimal equivalent meaning of the
gain register is
where the binary numbers have a value of either
zero or one (b0 corresponds to bit MSB-1, N = 22).
Self Calibration
The CS5529 offers both self offset and self gain
calibrations. For the self-calibration of offset, the
converter internally ties the inputs of the modulator
together and routes them to the VREF- pin as
shown in Figure 6. Also self offset calibration re-
quires that VREF- be tied to a fixed voltage be-
tween VA+ and VA-. For self-calibration of gain,
the differential inputs of the modulator are connect-
ed to VREF+ and VREF- as shown in Figure7.
System Calibration
For the system calibration functions, the user must
input signals which represent system ground and
system full scale to the converter. When a system
offset calibration is performed a ground reference
signal must be applied to the converter (see Figure
8). When a system gain calibration is performed,
the user must input a signal representing the posi-
tive full scale point as shown in Figure 9. In either
case, calibration signals must be within the speci-
fied calibration limits for each specific calibration
step (refer to the System Calibration Specifica-
23(MSB)
22
21
20
19
18
1716151413
12
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
0
0
0
0
0
0
0
0000
0
11
10
9
8
7
6
5
4321
0
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
0
0
0
0
0
0
0
0000
0
Db
MSB
2
1
b
(
0
2
0
b
1
2
1
… b
N
2
N
– )
++
+
+
b
MSB
2
1
b
i
2
i
i
0
=
N
+
==
AIN+
AIN-
S1
OPEN
+
-
S2
OPEN
S4
CLOSED
VREF-
Figure 6. Self Calibration of Offset.
AIN+
AIN-
OPEN
+
-
OPEN
CLOSED
VREF+
CLOSED
VREF-
+
-
Reference
Figure 7. Self Calibration of Gain.
+
-
External
Connections
0V +
-
AIN+
AIN-
Figure 8. System Calibration of Offset.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com