ST8034AT datasheet(16/39 Pages) STMICROELECTRONICS

16 / 39 page

DocID024587 Rev 4

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ST8034T, ST8034AT, ST8034P, ST8034C

Electrical characteristics

Delay time

Between RSTIN and RST; RST

enabled

s

VOL

Output voltage low

IOL = 200 A, VCC = 5 V

0.3

IOL = 200 A, VCC = 3 V

0.2

IOL = 20 mA (current limit)

VCC - 0.4

VCC

VOH

Output voltage high

IOH = -200 A

0.9 VCC

VCC

IOH = -20 mA (current limit)

0.4

Rise time

CL = 100 pF

0.1

s

Fall time

CL = 100 pF

0.1

s

Clock output to the card (CLK pin)

Output voltage in shutdown

mode

No load

0.1

IO = 1 mA

0.3

Output current in shutdown

mode

CLK connected to GND

-1

VOL

Output voltage low

IOL = 200 A0

0.3

IOL = 70 mA (current limit)

VCC -0.4

VCC

VOH

Output voltage high

IOH = -200 A

0.9 VCC

VCC

IOH = -70 mA (current limit)

0.4

Rise time(3)

CL = 30 pF

Fall time(3)

CL = 30 pF

fCLK

Frequency on CLK pin

Operational

MHz

Duty cycle(3)

CL = 30 pF

Slew rate (rise and fall,

CL = 30 pF)

VCC = 5 V

0.2

V/ns

VCC = 3 V

0.12

Card detection input (PRES pin)(4)

VIL

Input voltage low

-0.3

0.3

VDD(INTF)

VIH

Input voltage high

0.7

VDD(INTF)

+ 0.3

VHYS

Hysteresis

0.14

VDD(INTF)

IIL

Input current low

0 < VIL < VDD(INTF)

A

IIH

Input current high

0 < VIH < VDD(INTF)

A

1. TA = 25 °C, VDD = 3.3 V, VDDP = 5 V, VDD(INTF) = 3.3 V, fXTAL = 10 MHz, unless otherwise noted.

2. With an internal 9 k

 pull-up resistor to VCC.

3. For rise and fall times and duty cycle definitions, see Figure 7 on page 21.

4. PRES is active low, with an internal current source of 1.25

A to VDD(INTF).

Table 8. Card interface (continued)

Symbol

Parameter

Test conditions(1)

Min.

Typ.

Max.

Unit

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