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ST8034AT 数据表(PDF) 24 Page - STMicroelectronics

部件名 ST8034AT
功能描述  16-pin smartcard interfaces
PDF  39 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST8034AT 数据表(HTML) 24 Page - STMicroelectronics

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ST8034T, ST8034AT, ST8034P, ST8034C
Functional description
6.3
Clock circuits
6.3.1
ST8034T and ST8034AT clock possibilities
The clock signal for the card (CLK output) is either provided by an external clock signal
connected to the XTAL1 pin or generated by a crystal connected between the XTAL1 and
XTAL2 pins. The ST8034 device automatically detects if an external clock is connected to
the XTAL1, which eliminates the need for a separate clock source selection pin. Automatic
clock source detection is performed on each activation command (falling edge of
CMDVCC). The presence of an external clock on the XTAL1 pin is checked during a time
window defined by the internal oscillator. If the external clock is detected, the crystal
oscillator is stopped. If the clock is not detected, the crystal oscillator is started. When the
external clock is used, the clock signal must be present on the XTAL1 pin before the
CMDVCC falling edge. If the external clock is used, connect it to XTAL1 input and leave the
XTAL2 pin floating. The XTAL1 pin cannot be left floating, either a crystal or an external
clock source needs to be connected.
Figure 11. External clock usage
The clock frequency is selected using the CLKDIV pin and is either fXTAL/2 or fXTAL/4 on the
ST8034T device or fXTAL or fXTAL/2 on the ST8034AT, as shown in Table 13. The frequency
change is synchronous, meaning that after transition on the CLKDIV input, the present clock
period is completed and after that the new whole clock period starts, therefore no clock
period is shortened during the frequency switchover.
If an external crystal is used, the duty cycle on the CLK pin should be between 45% and
55%. If an external clock is connected to the XTAL1 pin, its duty cycle must be between 48%
and 52% so that the CLK output duty cycle is between 45% and 55%.
Table 13. ST8034T and ST8034AT clock frequency selection
CLKDIV pin level
CLK frequency
ST8034T
ST8034AT
High
fXTAL/2
fXTAL/2
Low
fXTAL/4
fXTAL



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