 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
EPC901 数据表(PDF) 8 Page - Espros Photonics corp |
|
|
|||||||||||||||||||||||||||||
EPC901 数据表(HTML) 8 Page - Espros Photonics corp |
|
|
8 / 37 page  3.5. Timing parameters Parameter Description Min Typ Max Unit TSTARTUP Start-up time after applying external supply/supplies (includes ramp-up of charge pump) 10 ms TCP_UP Charge pump power-up time: time from changing the bit CP_PD from 1 to 0 until chip is operational (internal VDD5V) 5 ms TWAKE_UP Wake-up time from Power-Save mode 7 12 µs f OSC Oscillator clock frequency at nominal trim value (OSC_TRIM_REG at default value) room temperature 22.4 36 48 MHz -20°C < TA < 65°C 18 36 58 MHz f OSC_MAX_TRIM Frequency of oscillator clock that can be achieved through trim- ming 3 at room temperature. 32 MHz TSU,CONF Setup time of configuration pins with respect to rising edge of read pulse 50 ns TH,CONF Hold time of configuration pins with respect to rising edge of read pulse 3 Oscillator clock cycles TSHUTTER Pulse width of SHUTTER signal 5 Oscillator clock cycles TFLUSH Flush period 1 30 32 Oscillator clock cycles TSHIFT Shift period 1 24 26 Oscillator clock cycles TRD_PULSE Pulse width of Read Pulse 3 Oscillator clock cycles TCDS CDS operation 37 Oscillator clock cycles TSTORE Duration how long a frame may be stored in the frame-store 10 ms TRD_CLK Period of the read clock 18.5 10'000 ns fREAD READ clock rate (the inverse of TRD_CLK) 2 0.1 54 MHz D READ clock duty cycle @ f READ max 45 50 55 % TH,VIDEO Period during which the output of the video amplifier is held sta- ble after the last read clock edge 50 µs TPERIOD,FLUSH Periodicity of the periodic flush operation 4 100 ms TPULSE,CLR_DATA Pulse width on CLR_DATA 3 Oscillator clock cycles BI2C I2C transmission rate 400 kbit/s Notes: 1 By measuring the frequency of the internal clock oscillator (see section 9.), the duration of the internal flush and shift periods can be cal- culated exactly. 2 To achieve the maximum clock frequency, the duty cycle of the read clock has to be 50% with a maximal tolerance of ±5%. 3 The internal oscillator must not be trimmed to a frequency higher than 50MHz. 4 Refer to section 5.6. for more details. 3.6. Absolute maximum ratings Description Conditions Power supply voltage (VDD) -0.3V to +5V Voltage to any Pin -0.3 to VDD +0.3V Storage Temperature Range (TS) -40°C to +85°C Relative humidity 0 to 95% non-condensing ESD rating all pins except VDD7V0 vs. VDD1V8: HBM class 2 ( 2kV to <4kV, JEDEC) Pin VDD7V0 vs. VDD1V8: HBM class 1B (500V to <1kV, JEDEC) Note: Pin VDD7V0 is in the final circuit loaded with 2.2µF low ESR capacitor. © 2016 ESPROS Photonics Corporation Characteristics subject to change without notice 8 / 37 Datasheet_epc901-V5.6 www.espros.com |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
