4. Chip configuration

The epc901 IC can be configured either by the configuration pins or through I2C commands. At power-up or software reset, the status of

the configuration pins are read and used to operate the chip. The configuration can later on be changed with I2C commands (refer to Table

9). Make sure that the bit RD_CONF_CTRL is set properly.

4.1. Configuration pin description

Pin Name

Low (GND)

High-Z

High (VDD)

Comments

RD_DIR

Pixel 0 .. 1023

Pixel 1023 .. 0

ROI_SEL

Pixel 0 .. 1023

Pixel 256 .. 767 Readout region of the pixel array

Gain

2

1

4

Multiplier for the conversion gain

HOR_BIN

2 pixel

1 pixel

4 pixel

Defines horizontal binning. Binning here means averaging over 2 or 4 pix-

els in the voltage domain (not charge domain!) e.g. for HOR_BIN=H, pix-

els 0..3, 4..7, 8..11 etc. are averaged as follows

V

V

[i]+V [i+1]+V [i+2]+V [i+3 ]

4

, i = 0, 3, 7, .., 1020

Binning can be used to reduce the read-out time by the binning factor.

Note: Binning 2 (HOR_BIN = 0) is not applicable for single-ended mode.

VIDEO_CM

Single ended

Differential

n/a

Refer also to section 11.1. Circuit for differential mode

DATA_RDY

Charge pump

on

N/A

Charge pump

off

Refer to section 4.3.

BW0

X

Max. video bandwidth

(referred to as 16MHz, see section 4.4. Frequency response setting)

BW1

X

BW0

X

High video bandwidth

(referred to as 8MHz)

BW1

X

BW0

X

Low video bandwidth

(referred to as 4MHz)

BW1

X

BW0

X

Min. video bandwidth

(referred to as 1MHz, see section 4.4. Frequency response setting)

BW1

X

Table 3: Configuration pin description

Notes:

•

The shaded values are recommended for typical and easy to use applications.

•

The bandwidth of the video amplifier (configured through BW and VIDEO_GBW_SEL_REG) affects the current consumption of

the chip and the noise at the output. The lower the bandwidth the lower the noise and the lower the current consumption. Thus, it

is a good concept to keep the bandwidth as low as possible.

•

The configuration pins are read into the registers ACQ_TX_CONF_EFF and BW_VIDEO_CONF_EFF (and become effective)

upon reset (i.e. power-up or software reset). In case RD_CONF_CTRL is left at default setting 0 (see Table 9), the configuration

pins are also read upon the rising edge of READ (refer to section 5.4.).

•

The re-sampled values of the configuration pins take effect immediately if the configuration is controlled by the configuration

pins.

•

The configuration set by the configuration pins can be overwritten by writing to the registers ACQ_TX_CONF and/or

BW_VIDEO_CONF through I2C (see section 10.). The overwrite functionality has to be enabled by setting RD_CONF_CTRL=1

(see Table 9).

•

The CS0 and CS1 pin configuration are described in section 10.1.1. Device addressing.

© 2016 ESPROS Photonics Corporation

Characteristics subject to change without notice

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Datasheet_epc901-V5.6

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