Wide Brightness Range

CCFL Backlight Controllers

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9

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NAME

PIN

MAX1739

MAX1839

FUNCTION

1

REF

REF

2V Reference Output. Bypass to GND with 0.1

µF. Forced low during shutdown.

2

MINDAC

MINDAC

DAC Zero-Scale Input. VMINDAC sets the DAC’s minimum scale output voltage.

Disable DPWM by connecting MINDAC to VL.

3

CCI

CCI

GMI Output. Output of the current loop GMI amplifier that regulates the CCFL current.

Typically bypass to GND with 0.1

µF.

4

CCV

CCV

GMV Output. Output of the voltage loop GMV amplifier that regulates the maximum

average primary transformer voltage. Typically bypass to GND with 3300pF.

5

SH/SUS

SH

Logic Low Shutdown Input in Analog Interface Mode. SMBus suspends input in SMBus

interface mode (MAX1739 only).

6

CRF/SDA

CRF

5-Bit ADC Reference Input in Analog Interface Mode. Bypass to GND with 0.1

µF. SMBus serial

data input/open-drain output (MAX1739 only) in SMBus interface mode.

7

CTL/SCL

CTL

CCFL Brightness Control Input in Analog Interface Mode. SMBus serial clock input

(MAX1739 only) in SMBus interface mode.

8

MODE

MODE

Interface Selection Input and Sync Input for DPWM Chopping (see Synchronizing the

DPWM Frequency). The average voltage on the MODE pin selects one of three CCFL

brightness control interfaces:

1) MODE = VL, enables SMBus serial interface (MAX1739 only).

2) MODE = GND, enables the analog interface (positive scale analog interface mode);

VCTL/SCL = 0 means minimum brightness.

3) MODE = REF, enables the analog interface (negative scale analog interface mode);

VCTL/SCL = 0 means maximum brightness.

9

CSAV

CSAV

Current-Sense Input. Input to the GMI error amplifier that drives CCI.

10

CTFB

CTFB

Center-Tap Voltage Feedback Input. The average VCTFB is limited to 0.6V.

11

SYNC

SYNC

Royer Synchronization Input. Falling edges on SYNC force DH on and toggle the DL1

and DL2 drivers. Connect directly to the Royer center tap.

12

DL2

DL2

Low-Side N-Channel MOSFET 2 Gate Drive. Drives the Royer oscillator switch. DL1 and

DL2 have make-before-break switching, where at least one is always on. Falling edges

on SYNC toggle DL1 and DL2 and turn DH on.

13

DL1

DL1

Low-Side N-Channel MOSFET 1 Gate Drive

14

CS

CS

Current-Sense Input (Current Limit). The current-mode regulator terminates the switch

cycle when VCS exceeds (VREF - VCCI).

15

GND

GND

System Ground

16

VL

VL

5.3V Linear Regulator Output. Supply voltage for most of the internal circuits. Bypass

with 1

µF capacitor to GND. Can be connected to VBATT if VBATT < 5.5V.

17

BST

BST

High-Side Driver Bootstrap Input. Connect through a diode to VL and bypass with 0.1

µF

capacitor to LX.

18

LX

LX

High-Side Driver Ground Input

19

DH

DH

High-Side Gate Driver Output. Falling edges on SYNC turn on DH.

20

BATT

BATT

Supply Input. Input to the internal 5.3V linear regulator that powers the chip.

Pin Description