MAX1739EEP datasheet(14/26 Pages) MAXIM

14 / 26 page

Wide Brightness Range

CCFL Backlight Controllers

______________________________________________________________________________________

brightness code of ob00000 corresponds to a 9.375%

DPWM duty cycle, and a brightness code of ob11111

corresponds to a 100% DPWM duty cycle. The duty

cycle changes by 3.125% per step, except codes

ob00000 to ob00011 all produce 9.375% (Figure 3).

To disable DPWM and always use 100% duty cycle, set

VMINDAC to VL. Note that with DPWM disabled, the

equations above should assume VMINDAC = 0 instead

of VMINDAC = VL. Table 2 lists MINDAC’s functionality,

and Table 3 shows some typical settings for the bright-

ness adjustment.

In normal operation, VMINDAC is set between 0 and

VREF, and the MAX1739/MAX1839 use both lamp cur-

rent control and DPWM control to vary the lamp bright-

ness (Figure 4). In this mode, lamp current control

regulates the average lamp current during a DPWM on-

cycle and not the overall average lamp current.

Analog Interface and Brightness Code

The MAX1739/MAX1839 analog interface uses an inter-

nal ADC with 1-bit hysteresis to generate the brightness

code used to dim the lamp (see Dimming Range).

CTL/SDA is the ADC’s input, and CRF/SCL is its refer-

ence voltage. The ADC can operate in either positive-

scale ADC mode or negative-scale ADC mode. In

positive-scale ADC mode, the brightness code increas-

es from 0 to 31 as VCTL increases from 0 to VCRF. In

negative-scale mode, the brightness scale decreases

from 31 to 0 as VCTL increases from 0 to VCRF (Figure 5).

The analog interface’s internal ADC uses 1-bit hystere-

sis to keep the lamp from flickering between two codes.

VCTL’s positive threshold (VCTL(TH)) is the voltage

required to transition the brightness code as VCTL

increases and can be calculated as follows:

VCTL(TH) = (n + 2) / 33 VCRF

(positive-scale ADC mode, MODE = GND)

VCTL(TH) = (33 - n) / 33 VCRF

(negative-scale ADC mode, MODE = REF)

where n is the current selected brightness code. VCTL’s

negative threshold is the voltage required to transition

the brightness code as VCTL decreases and can be

calculated as follows:

VCTL(TH) = n / 33 VCRF

(positive-scale ADC mode, MODE = GND)

VCTL(TH) = (31 - n) / 33 VCRF

(negative-scale ADC mode, MODE = REF)

Figure 5 shows a graphic representation of the thresh-

olds. CRF/SDA’s and CTL/SCL’s input voltage range is

2.7V to 5.5V.

MINDAC = VL

DPWM disabled (always on 100% duty cycle). Operates in lamp current control only.

(Use VMINDAC = 0 in the equations.)

MINDAC = REF

DPWM control enabled, duty cycle ranges from 9% to 100%. Lamp current control is disabled

(always maximum current).

≤ VMINDAC < VREF

The device uses both lamp current control and DPWM.

Table 2. MINDAC Functionality

100

012

BRIGHTNESS CODE

DPWM SETTINGS

Figure 3. DPWM Settings

100

012

BRIGHTNESS CODE

COMBINED POWER LEVEL

(BOTH DPWM AND

LAMP CONTROL CURRENT)

Figure 4. Combined Power Level

MAX1739EEP 数据表(PDF) 14 Page - Maxim Integrated Products

MAX1739EEP 数据表(HTML) 14 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表下载