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MIPSZ2012D3R3 数据表(PDF) 30 Page - STMicroelectronics

部件名 MIPSZ2012D3R3
功能描述  High-performance class-G stereo headphone amplifier with I2C volume control
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

MIPSZ2012D3R3 数据表(HTML) 30 Page - STMicroelectronics

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Application information
TS4621B
30/48
Doc ID 022194 Rev 2
4.1.5
Summary of output impedance
4.2
Wake-up and standby time definition
The wake-up time of the TS4621B is guaranteed at 12 ms typical (refer to Chapter 3:
Electrical characteristics). However, since the TS4621B is activated with an I2C bus, the
wake-up start procedure is as follows.
1.
The master sends a start bit.
2.
The master sends the device address.
3.
The slave (TS4621B) answers by an acknowledge bit.
4.
The master sends the register address.
5.
The slave (TS4621B) answers by an acknowledge bit.
6.
The master sends the output mode configuration (CR1).
7.
If the TS4621B was previously in standby mode, the wake-up starts on the falling edge
of the eighth clock signal (SCL) corresponding to the CR1 byte.
8.
After 12 ms (de-pop sequence time), the TS4621B outputs are operational.
The standby time is guaranteed as 100 µs typical (refer to Chapter 3). However, since the
TS4621B is de-activated with an I2C bus, the standby time operates as follows.
1.
The master sends a start bit.
2.
The master sends the device address.
3.
The slave (TS4621B) answers by an acknowledge bit.
4.
The master sends the register address.
5.
The slave (TS4621B) answers by an acknowledge bit.
6.
The master sends the output mode configuration (CR1), which corresponds, in this
case, to standby mode.
7.
The standby time starts on the falling edge of the eighth clock signal (SCL)
corresponding to the CR1 byte.
8.
After 100 µs, the TS4621B is in standby mode.
Table 13.
Summary table for output impedance vs. output mode
SWS
HiZ
HP_EN
Output impedance
Maximum voltage allowed
on output pin
1
0
0
20 to 40
Ω
Less than
± 100 mV
1
0
1
20 to 40
Ω
Less than
± 100 mV
1
1
0
about 10 k
Ω
-0.3 V to AVdd
1
1
1
about 10 k
Ω
-0.3 V to AVdd
0
0
0
20 to 40
Ω
Less than
± 100 mV
0
0
1
Less than 1
Ω
Not applicable
0
1
0
See Figure 18
-1.8 to +1.8 V
0
1
1
See Figure 18
-1.8 to +1.8 V



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