R5F100GL datasheet(62/202 Pages) RENESAS

62 / 202 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

C)

Page 62 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

(TA =

40 to +85C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

ILIH1

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P67,

P70 to P77, P80 to P87,

P90 to P97, P100 to P106,

P110 to P117, P120,

P125 to P127, P140 to P147

VI = EVDD0

A

ILIH2

P20 to P27, P137,

P150 to P156, RESET

VI = VDD

A

In input port or

external clock

input

A

Input leakage

current, high

ILIH3

P121 to P124

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

VI = VDD

In resonator

connection

A

ILIL1

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P67,

P70 to P77, P80 to P87,

P90 to P97, P100 to P106,

P110 to P117, P120,

P125 to P127, P140 to P147

VI = EVSS0

1

A

ILIL2

P20 to P27, P137,

P150 to P156, RESET

VI = VSS

1

A

In input port or

external clock

input

1

A

Input leakage

current, low

ILIL3

P121 to P124

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

VI = VSS

In resonator

connection

10

A

On-chip pll-up

resistance

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P64 to P67,

P70 to P77, P80 to P87,

P90 to P97, P100 to P106,

P110 to P117, P120,

P125 to P127, P140 to P147

VI = EVSS0, In input port

100



Remark

Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the

port pins.

R5F100GL 数据表(PDF) 62 Page - Renesas Technology Corp

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R5F100GL 数据表(PDF) 62 Page - Renesas Technology Corp

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