HT82B40A datasheet(18/54 Pages) HOLTEK

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HT82B40R/HT82B40A

Rev. 1.70

November 5, 2014

its correct operation, a process that is normally carried

out during program initialization.

To choose which of the three modes the timer is to oper-

ate in, either in the timer mode, the event counting mode

or the pulse width measurement mode, bits 7 and 6 of

the Timer Control Register, which are known as the bit

pair T0M1/T0M0 or T1M1/T1M0 respectively, depend-

ing upon which timer is used, must be set to the required

logic levels. The timer-on bit, which is bit 4 of the Timer

Control Register and known as T0ON or T1ON, depend-

ing upon which timer is used, provides the basic on/off

control of the respective timer. Setting the bit high allows

the counter to run, clearing the bit stops the counter. If

the timer is in the event count or pulse width measure-

ment mode, the active transition edge level type is se-

lected by the logic level of bit 3 of the Timer Control

upon which timer is used.

Configuring the Timer Mode

In this mode, the Timer/Event Counter can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer

Control Register must be set to the correct value as

shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode the internal clock, fSYS/4 is used as the in-

ternal clock for the Timer/Event Counters. After the

other bits in the Timer Control Register have been

setup, the enable bit T0ON or T1ON, which is bit 4 of the

Timer Control Register, can be set high to enable the

Timer/Event Counter to run.Each time an internal clock

cycle occurs, the Timer/Event Counter increments by

one. When it is full and overflows, an interrupt signal is

generated and the Timer/Event Counter will reload the

value already loaded into the preload register and con-

tinue counting. The interrupt can be disabled by ensur-

ing that the Timer/Event Counter Interrupt Enable bit in

the Interrupt Control Register, INTC, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair, T0M1/T0M0

or T1M1/T1M0, in the Timer Control Register must be

set to the correct value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode, the external timer pin, TMR0 or TMR1, is

used as the Timer/Event Counter clock source, however

it is not divided by the internal prescaler. After the other

bits in the Timer Control Register have been setup, the

enable bit T0ON or T1ON, which is bit 4 of the Timer

Control Register, can be set high to enable the

Timer/Event Counter to run. If the Active Edge Select bit

T0E or T1E, which is bit 3 of the Timer Control Register,

is low, the Timer/Event Counter will increment each time

the external timer pin receives a low to high transition. If

the Active Edge Select bit is high, the counter will incre-

ment each time the external timer pin receives a high to

low transition. When it is full and overflows, an interrupt

signal is generated and the Timer/Event Counter will re-

load the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer/Event Counter Interrupt Enable

bit in the Interrupt Control Register, INTC, is reset to

zero.

As the external timer pin is shared with an I/O pin, to en-

sure that the pin is configured to operate as an event

counter input pin, two things have to happen. The first is

to ensure that the Operating Mode Select bits in the

Timer Control Register place the Timer/Event Counter in

the Event Counting Mode, the second is to ensure that

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart

HT82B40A 数据表(PDF) 18 Page - Holtek Semiconductor Inc

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