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HT82B40A 数据表(PDF) 25 Page - Holtek Semiconductor Inc |
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HT82B40A 数据表(HTML) 25 Page - Holtek Semiconductor Inc |
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25 / 54 page  HT82B40R/HT82B40A Rev. 1.70 25 November 5, 2014 Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 RES reset during power-on 0 0 RES wake-up during Power Down 0 0 RES or LVR reset during normal operation 1 u WDT time-out reset during normal operation 1 1 WDT time-out reset during Power Down Note: ²u² stands for unchanged The following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller in- ternal registers. Register Reset (Power-on) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB Reset (Normal) USB Reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx BP 0000 0000 0000 0000 0000 0000 0000 0000 00u0 00uu 0000 0000 0000 0000 ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000H 0000H 0000H 0000H 0000H 0000H 0000H TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 STATUS --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx TMR0C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- uu-u u--- uu-u u--- TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- uu-u u--- uu-u u--- PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 |
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