N79E352APG datasheet(21/135 Pages) ETC2

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Preliminary N79E352/N79E352R Data Sheet

Publication Release Date: Jul, 29, 2009

- 21 -

Revision A06

8.2 SFR Detail Bit Descriptions

PORT 0

Bit:

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

Mnemonic: P0

Address: 80h

Port 0 is an open-drain bi-directional I/O port. This port provides a multiplexed low order address/data

bus during accesses to external memory. The ports also support alternate input function for Keyboard

pins (KB0-7).

BIT

NAME

FUNCTION

P0.7

AD7 or KB7 or I/O pin by alternative.

P0.6

AD6 or KB6 or I/O pin by alternative.

P0.5

AD5 or KB5 or I/O pin by alternative.

P0.4

AD4 or KB4 or I/O pin by alternative.

P0.3

AD3 or KB3 or I/O pin by alternative.

P0.2

AD2 or KB2 or I/O pin by alternative.

P0.1

AD1 or KB1 or I/O pin by alternative.

P0.0

AD0 or KB0 or I/O pin by alternative.

Note: The initial value of the port is set by CONFIG0.PRHI bit. The default setting for CONFIG0.PRHI =1 which the alternative

function output is turned on upon reset. If CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the

alternative function output.

STACK POINTER

Bit:

SP.7

SP.6

SP.5

SP.4

SP.3

SP.2

SP.1

SP.0

Mnemonic: SP

Address: 81h

BIT

NAME

FUNCTION

7-0

SP.[7:0]

The Stack Pointer stores the Scratch-pad RAM address where the stack begins.

In other words it always points to the top of the stack.

DATA POINTER LOW

Bit:

DPL.7

DPL.6

DPL.5

DPL.4

DPL.3

DPL.2

DPL.1

DPL.0

Mnemonic: DPL

Address: 82h

BIT

NAME

FUNCTION

7-0

DPL.[7:0]

This is the low byte of the standard 8052 16-bit data pointer.

DATA POINTER HIGH

Bit:

N79E352APG 数据表(PDF) 21 Page - List of Unclassifed Manufacturers

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