N79E352APG datasheet(9/135 Pages) ETC2

9 / 135 page

Preliminary N79E352/N79E352R Data Sheet

Publication Release Date: Jul, 29, 2009

- 9 -

Revision A06

5. PIN DESCRIPTIONS

SYMBOL

Alternate

Function 1

Alternate

function 2

Type

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the

processor to execute out of external ROM. It should

be kept high to access internal ROM. The ROM

address and data will not be present on the bus if

EA pin is high and the program counter is within

internal ROM area. Otherwise they will be present on

the bus.

PSEN

PROGRAM STORE ENABLE: PSEN enables the

external ROM data onto the Port 0 address/data bus

during fetch and MOVC operations. When internal

ROM access is performed, no PSEN strobe signal

outputs from this pin.

ALE

ADDRESS LATCH ENABLE: ALE is used to enable

the address latch that separates the address from

the data on Port 0.

XTAL1

P5.1

I/O

CRYSTAL1: This is the crystal oscillator input. This

pin may be driven by an external clock or

configurable i/o pin, P5.1.

XTAL2

P5.0

I/O

CRYSTAL2: This is the crystal oscillator output. It is

the inversion of XTAL1. Also a configurable i/o pin,

P5.0.

VDD

POWER SUPPLY: Supply voltage for operation.

VSS

GROUND: Ground potential.

RST

RESET: A high on this pin for two machine cycles

while the oscillator is running resets the device.

P0.0

KB0

AD0

I/O

PORT0:

Support 4 mode output and 2 mode input.

Multifunction pins for AD0-7and KB0-7.

P0.1

KB1

AD1

I/O

P0.2

KB2

AD2

I/O

P0.3

KB3

AD3

I/O

P0.4

KB4

AD4

I/O

P0.5

KB5

AD5

I/O

P0.6

KB6

AD6

I/O

P0.7

KB7

AD7

I/O

P1.0

I/O

PORT1:

Support 4 mode output and 2 mode input.

Multifunction pins for SDA & SCL (I2C), T2, T2EX

and PWM0-1.

P1.1

T2EX

I/O

P1.2

SDA

I/O

P1.3

SCL

I/O

P1.4

PWM0

I/O

P1.5

PWM1

I/O

P1.6

ICPDAT

I/O

P1.7

ICPCLK

I/O

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