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N79E352APG 数据表(PDF) 39 Page - List of Unclassifed Manufacturers |
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N79E352APG 数据表(HTML) 39 Page - List of Unclassifed Manufacturers |
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39 / 135 page ![]() Preliminary N79E352/N79E352R Data Sheet Publication Release Date: Jul, 29, 2009 - 39 - Revision A06 7~6 CD1~0 Clock Divide Control. These bit selects the number of clocks required to generate one machine cycle. There are three modes including divide by 4, 64 or 1024. Switching between modes must first go back devide by 4 mode. For instance, to go from 64 to 1024 clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle, and then from 4 to 1024 clocks/machine cycle. CD1, CD0 Clocks/machine Cycle 0 X 4 1 0 64 1 1 1024 5 SWB Switchback Enable. Setting this bit allows an enabled external interrupt or serial port/I2C activity to force the CD1, CD0 to divide by 4 state (0,X). The device will switch modes at the start of the jump to interrupt service routine while an external interrupt is enabled and actually recognized by microcontroller. While a serial port/I2C reception, the switchback occurs at the start of the instruction following the falling edge of the start bit. Note: Changing SWB bit is ignored during serial port/I2C activities. 4~3 - Reserved. 2 ALE-0FF This bit disables the expression of the ALE signal on the device pin during all on- board program and data memory accesses. External memory accesses will automatically enable ALE independent of ALE-OFF. 0 = ALE expression is enable. 1 = ALE expression is disable. 1~0 - Reserved. STATUS Bit: 7 6 5 4 3 2 1 0 - - - - - - SPTA0 SPRA0 Mnemonic: STATUS Address: C5h BIT NAME FUNCTION 7-2 - Reserved. 1 SPTA0 Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data. It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1. 0 SPRA0 Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1. NVM LOW BYTE ADDRESS Bit: 7 6 5 4 3 2 1 0 |
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