2

Integrated

Circuit

Systems, Inc.

ICS954119

Advance Information

0875—05/24/04

Pin Description

PIN # PIN NAME

PIN

TYPE

DESCRIPTION

1

GND

PWR

Ground pin.

2

PCICLK3

OUT

PCI clock output.

3

PCICLK4

OUT

PCI clock output.

4

PCICLK5

OUT

PCI clock output.

5

GND

PWR

Ground pin.

6

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

7

PCICLK_F0

OUT

Free running PCI clock not affected by PCI_STOP# .

8

FSLA/PCICLK_F1

I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock

output.

9

FSLB/PCICLK_F2

I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock

output.

10

VDD48

PWR

Power pin for the 48MHz output.3.3V

11

**SEL24_48#/24_48MHz

I/O

Latched select input for 24/48MHz output / 24/48MHz clock output.

1=24MHz, 0 = 48MHz.

12

USB_48MHz

OUT

48.00MHz USB clock

13

GND

PWR

Ground pin.

14

DOTT_ 96MHz

OUT

True clock of differential pair for 96.00MHz DOT clock.

15

DOTC_96MHz

OUT

Complement clock of differential pair for 96.00MHz DOT clock.

16

Vtt_PwrGd#/PD

IN

Vtt_PwrGd# is an active low input used to determine when latched inputs

are ready to be sampled. PD is an asynchronous active high input pin

used to put the device into a low power state. The internal clocks, PLLs

and the crystal oscillator are stopped.

17

PCIEXT0

OUT

True clock of differential PCI_Express pair.

18

PCIEXC0

OUT

Complement clock of differential PCI_Express pair.

19

VDDPCIEX

PWR

Power supply for PCI Express clocks, nominal 3.3V

20

GND

PWR

Ground pin.

21

PCIEXT1

OUT

True clock of differential PCI_Express pair.

22

PCIEXC1

OUT

Complement clock of differential PCI_Express pair.

23

PCIEXT2

OUT

True clock of differential PCI_Express pair.

24

PCIEXC2

OUT

Complement clock of differential PCI_Express pair.

25

GND

PWR

Ground pin.

26

SRCCLKT

OUT

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

27

SRCCLKC

OUT

Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

28

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal