3

Integrated

Circuit

Systems, Inc.

ICS954119

Advance Information

0875—05/24/04

Pin Description

PIN # PIN NAME

TYPE

DESCRIPTION

29

GND

PWR

Ground pin.

30

PCIEXC3

OUT

Complement clock of differential PCI_Express pair.

31

PCIEXT3

OUT

True clock of differential PCI_Express pair.

32

PCIEXC4

OUT

Complement clock of differential PCI_Express pair.

33

PCIEXT4

OUT

True clock of differential PCI_Express pair.

34

VDDPCIEX

PWR

Power supply for PCI Express clocks, nominal 3.3V

35

VDDA

PWR

3.3V power for the PLL core.

36

GNDA

PWR

Ground pin for the PLL core.

37

IREF

OUT

This pin establishes the reference current for the differential current-mode

output pairs. This pin requires a fixed precision resistor tied to ground in

order to establish the appropriate current. 475 ohms is the standard value.

38

GND

PWR

Ground pin.

39

CPUCLKC1

OUT

Complimentary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

40

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

41

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

42

CPUCLKC0

OUT

Complimentary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

43

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

44

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

45

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

46

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

47

X2

OUT

Crystal output, Nominally 14.318MHz

48

X1

IN

Crystal input, Nominally 14.318MHz.

49

GND

PWR

Ground pin.

50

REF1

OUT

14.318 MHz reference clock.

51

REF0/FSLC

I/O

14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency

selection. Refer to input electrical characteristics for Vil_FS and Vih_FS

values.

52

Reset#

OUT

Real time system reset signal for frequency gear ratio change or watchdog

timer timeout. This signal is active low.

53

PCICLK0

OUT

PCI clock output.

54

PCICLK1

OUT

PCI clock output.

55

PCICLK2

OUT

PCI clock output.

56

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V