2004 November 8

5

LPC2124

Philips Semiconductors

Single Chip 32-bit Microcontroller

Erratasheet

ADC.5

Edge triggered ADC conversion start error

Introduction:

When the START field of the ADCR register contains 010-111 the EDGE bit in ADCR will determine

whether a conversion is started on a rising or falling edge of the selected CAP/MAT signal. EDGE=0

selects rising edge detection, EDGE=1 selects falling edge detection. (On CAP/MAT pin)

Problem:

If the state of the selected CAP/MAT signal is 1 and EDGE is set to detect rising edges (EDGE = 0)

or, if detection of falling edges is selected (EDGE = 1) and the state of the selected CAP/MAT signal

is 0, an ADC conversion will immediately be initiated when the START bits are written to. So the

first conversion behaves as a level triggered event rather than edge triggered.

Work-around:

Clear the selected CAP/MAT signal for EDGE = 0 or set the selected CAP/MAT signal for EDGE =

1 before writing 010-111 to START field. Alternatively, discard the first conversion after writing to

the start bits.

ADC.6

Writing to ADCR while conversion in progress

Introduction:

Writing to ADCR while a conversion is in progress should set the DONE bit and start a new

conversion.

Problem:

In actuality, if the ADCR is written to within 2.5 ADC_clock cycles, a new conversion is started but

the DONE bit is not set. If the ADCR is written to after 2.5 ADC_clocks, but within a conversion

time, the DONE bit is set within one ADC_clock and a new conversion is started.

work-around:

Do not write to ADCR until the conversion is complete.

SPI.1

Unintentional clearing of SPI interrupt flag

Introduction:

The SPI interrupt flag is set by the SPI interface to generate an interrupt. It is cleared by writing a

1 to this bit.

Problem:

A write to any register associated with the SPI peripheral will clear the SPI interrupt register.

work-around:

Avoid writing to SPI registers while transmissions are in progress or while SPI interrupts are

pending.

EXTINT.1

Corruption of VPBDIV via EXTPOLAR or EXTMODE

Introduction:

The VPBDIV register controls the rate of the VPB clock in relation to the processor clock.

EXTPOLAR and EXTMODE determine the operating parameters of the external interrupts.

Problem:

A write to either the external interrupt polarity register (EXTPOLAR) or the external interrupt mode

register (EXTMODE) will corrupt the VPBDIV register. A read of either EXTPOLAR or EXTMODE

will be corrupted BY the VPBDIV register. If VPBDIV is “1” or “2” prior to any write to EXTPOLAR

or EXTMODE, the CPU will hang up on the write to EXTPOLAR or EXTMODE.

work-around:

If VPBDIV is non-zero, write all zeroes to VPBDIV before reading or writing EXTMODE or

EXTPOLAR, then write the proper value back to VPBDIV. In most applications this is a known and

fixed value, but if there is a possibility of dynamic changes in VPBDIV, software will need to read

VPBDIV, write zero to VPBDIV, read or write EXTMODE and/or EXTPOLAR, and then rewrite the

value previously read from VPBDIV.