2004 November 8

4

LPC2124

Philips Semiconductors

Single Chip 32-bit Microcontroller

Erratasheet

ADC.1:

First two ADC conversions in burst mode from same channel

Introduction:

In burst mode the A/D converter does repeated conversions at the rate selected by the CLKS field

in the ADCR, scanning (if necessary) through the pins selected by 1s in the SEL field. The first

conversion after the start corresponds to the least-significant 1 in the SEL field, then higher

numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit.

Problem:

In burst conversion mode, the first two conversions (after setting the mode) will be of the same,

lowest-numbered, of the selected channels.

work-around:

Ignore the first conversion, always check the CHN bits to confirm the channel converted.

ADC.2:

First conversion from channel specified by previous SEL setting

Introduction:

The ADCR SFR contains bits to enable the ADC burst mode (BURST), start the conversion in

software control mode (START), and to select the channel to begin converting (SEL).

Problem:

In burst mode, If the BURST bit is set before or simultaneously to (using the STR instruction for

example), the SEL bits, then the first channel converted will correspond to the previous SEL bit

settings.

In software control mode (only when using external trigger), if the START bits are set before or

simultaneously to (using the STR instruction for example) the SEL bits, then the first channel

converted will correspond to the previous SEL bit settings.

work-around:

Set the BURST/START bit(s) after setting the SEL bits.

ADC.3:

Incorrect scan pattern

Introduction:

In hardware scan mode multiple ADC channels may be selected as part of the scan by selecting

the appropriate bits in the SEL field in the ADCR register.

Problem:

Certain hardware scanning patterns for the A/D Converter do not operate properly. Selecting

channel 2 only leads to alternate sampling of channels 2 and 3. Selecting channels 1 and 2 leads

to sampling channel 1 for the first conversion, then sampling channel 2 on every subsequent

conversion.

work-around:

None. Do not use the sampling patterns "channel 2 only" or "channels 1 and 2". This problem has

no effect on software conversion, nor on any other patterns other than the two noted above.

ADC.4

Global powerdown does not power down the ADC

Introduction:

Setting the PD bit (bit 1) in PCON stops all clocks and powers down the peripherals. The ADC is

powered down by clearing the PDN bit (bit 21) in the ADCR register, setting the bit powers up

(enables) the ADC.

Problem:

If the PDN in ADCR is set, setting the PD bit in PCON will not power down the ADC.

Work-around:

Clear the PDN bit in the ADCR SFR to turn off the ADC prior to setting the PD bit in PCON.