Serial-to-Parallel/Parallel-to-Serial Converters and

Load-Switch Controllers with SMBus Interface

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3

Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested.

Note 2: Supply current is specified for static state only.

Note 3: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it

violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus.

Note 4: Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams).

Note 5: A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge.

Note 7: Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions.

Note 8: Refer to Figure 4 for I/O setup and hold timing parameter definitions.

10% or 90% of SMBDATA

to 10% of the rising edge

of SMBCLK

Measured from 90% of the rising edge

of SMBCLK to 10% of the rising edge of

SMBDATA

Measured from 10% of the falling edge

of SMBDATA to 90% of the falling edge of

SMBCLK

Measured from 90% of the SMBCLK rising

edge to 90% of the SMBDATA falling edge

CONDITIONS

ns

500

µs

4

SMBus Stop-Condition Setup

Time

µs

4

Start-Condition Hold Time

µs

4.7

Start-Condition Setup Time

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

the rising edge of SMBCLK (Note 8)

Measured from SMBCLK rising edge to 10%

or 90% of I/O (Note 4)

Between stop and start conditions (Note 7)

Tested with a 10k

Ω pull-up resistor on

SMBDATA (Note 6)

(Notes 4, 5)

µs

15

I/O Data Valid to SMBCLK

Rising-Edge Setup Time

ns

100

SMBus Write to I/O_

Propagation Delay

µs

4.7

SMBus Bus-Free Time

µs

1

SMBCLK Falling Edge to

SMBus Data Valid Time

µs

0

SMBCLK Falling Edge to

SMBDATA Transition Hold Time

Measured from the 10% point of the falling

edge of SMBDATA to the 10% point of the

rising edge of SMBDATA (Note 7)

(Note 8)

µs

10

15

30

START-STOP Software-Interrupt

Pulse Width

µs

0

I/O Data Hold Time

1000

SMBDATA Valid to SMBCLK

Rising Edge Time, Slave

Clocking in Data

to 5.5V

to 4.5V

ELECTRICAL CHARACTERISTICS (continued)