AT75C310

10

Figure 9. Static Memory Write Cycle (LCD Mode, Two Wait States)

Table 8. Static Memory Write Cycle (LCD Mode, Two Wait States Timings

Symbol

Parameter

Min (ns)

Max (ns)

t

CSLCSH

Chip Select Low to Chip Select High Time

82.0

–

t

AVCSL

Address Valid to Chip Select Low Time

18.0

–

t

AVWL

Address Valid to Write Strobe Low Time

19.0

–

t

CSHAH

Address Hold Time after Chip Select High

21.0

–

t

WHAH

Address Hold Time after Write Strobe High

20.0

–

t

WLWH

Write Strobe Low to Write Strobe High Time

81.0

–

t

DVCSH

Data Setup Time before Chip Select High

79.0

–

t

DVWH

Data Setup Time before Write Strobe High

79.0

–

t

CSHDH

Data Hold Time after Write Chip Select High

21.0

–

t

WHDH

Data Hold Time after Write Strobe High

20.0

–

A

NCE3

D

NWR/NWEx