AT75C310

7

Figure 6. Static Memory Read Cycle (Zero Wait State)

Table 5. Static Memory Read Cycle (Zero Wait State) Timings

Symbol

Parameter

Min (ns)

Max (ns)

Chip Select Low to Chip Select High Time

40.0

–

t

RLRH

Read Strobe Low to Read Strobe High Time

19.0

–

t

RLDV1

Read Strobe Low to Data Valid Time – Standard

Read Mode

–

6.0

t

RLDV2

Read Strobe Low to Data Valid Time – Early Read

Mode

–

27.0

Chip Select Low to Data Valid

–

25.0

t

AVDV

Address Valid to Data Valid

–

24.0

t

BSLDV

Byte Select Low to Data Valid

–

26.0

Read Strobe High to Chip Select High

0

–

t

RHAH

Address Hold after Read Strobe High

0

–

t

RHBSH

Read Strobe High to Byte Select High

0

–

Data Hold after Read Strobe High

0

–

A

NCEx

NWEx

(Byte Select Mode)

D

NSOE

(Early Read Mode)

NSOE

(Standard Read Mode)