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AT75C310 数据表(PDF) 6 Page - ATMEL Corporation |
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AT75C310 数据表(HTML) 6 Page - ATMEL Corporation |
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6 / 17 page ![]() AT75C310 6 Figure 5. DRAM Refresh Cycle Table 4. DRAM Refresh Cycle Timings Symbol Parameter Min (ns) Max (ns) t RC Cycle Time 125.0 – t RAS RAS Pulse Width 82.0 – tRP RAS Precharge Time 42.0 – t CP CAS Precharge Time 19.0 – t RPC RAS Precharge before CAS 33.0 – tCSR CAS Setup before RAS 48.0 – t CHR CAS Hold after RAS 32.0 – t CRP CAS to RAS Precharge Time 49.0 – tWRP Write Enable Setup Time (Refresh Cycle) 91.0 – t WRH Write Enable Hold Time (Refresh Cycle) 32.0 – tRC tRP tRAS tRPC tCSR tCRP NDWE NCASx NRASx tRP tCP tCHR tWRH tWRP |
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