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13

TPA3136D2, TPA3136AD2

www.ti.com

SLOS938D – MAY 2016 – REVISED MARCH 2017

Product Folder Links: TPA3136D2 TPA3136AD2

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Copyright © 2016–2017, Texas Instruments Incorporated

Feature Description (continued)

where

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•

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(1)

9.3.4 Spread Spectrum and De-Phase Control

The TPA3136D2/TPA3136AD2 device has built-in spread spectrum control of the oscillator frequency and de-

phase of the PWM outputs to improve EMI performance. The spread spectrum schemes is internally fixed is

always turned on.

De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio

channels are inverted. De-phase does not affect the audio signal, or its polarity.

9.3.5 GVDD Supply

The GVDD Supply is used to power the gates of the output full bridge transistors. Add a 1-μF capacitor to ground

at this pin.

9.3.6 DC Detect

The TPA3136D2/TPA3136AD2 device has circuitry which will protect the speakers from DC current which might

occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect

fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to

shutdown by changing the state of the outputs to Hi-Z.

A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 24% (±10%) for

more than 950 msec at the same polarity. This feature protects the speaker from large DC currents or AC

currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up

until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and

negative inputs to avoid nuisance DC detect faults.

The minimum differential input voltage required to trigger the DC detect is 130 mV.

9.3.7 PBTL Select

The TPA3136D2/TPA3136AD2 device offers the feature of parallel BTL operation with two outputs of each

channel connected directly. If the PBTL (pin 14) is tied high, the positive and negative outputs of each channel

(left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie PBTL pin to VCC and

apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and RIGHT outputs

with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half bridges for

highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical Applications

section.

9.3.8 Short-Circuit Protection and Automatic Recovery Feature

The TPA3136D2/TPA3136AD2 device has protection from overcurrent conditions caused by a short circuit on the

output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs

are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by

cycling the SD pin through the low state.

If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD

pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit

protection latch.