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LPC2124 数据表(PDF) 19 Page - NXP Semiconductors

部件名 LPC2124
功能描述  Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP Flash with 10-bit ADC
PDF  34 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

LPC2124 数据表(HTML) 19 Page - NXP Semiconductors

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Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Product data
Rev. 03 — 22 December 2004
19 of 34
9397 750 13145
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.14.1
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.15 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.15.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.16 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the Watchdog will
generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog
within a predetermined amount of time.
6.16.1
Features
Internally resets chip if not periodically reloaded.
Debug mode.



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