LPC2124 datasheet(20/34 Pages) PHILIPS

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Philips Semiconductors

LPC2114/LPC2124

Single-chip 16/32-bit microcontrollers

Product data

Rev. 03 — 22 December 2004

20 of 34

9397 750 13145

• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to

be disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate Watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (tpclk × 256 × 4) to (tpclk × 232 × 4) in multiples of

tpclk × 4.

6.17 Real time clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use

little power, making it suitable for battery powered systems where the CPU is not

running continuously (Idle mode).

6.17.1

Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Programmable reference clock divider allows adjustment of the RTC to match

various crystal frequencies.

6.18 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2114/LPC2124. The Timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match

registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to

be used for more applications. For instance, multi-phase motor control typically

requires three non-overlapping PWM outputs with individual control of all three pulse

widths and positions.

Two match registers can be used to provide a single edge controlled PWM output.

One match register (MR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single

edge controlled PWM outputs require only one match register each, since the

repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM

outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0

match occurs.

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