ADA4841-1/ADA4841-2

Data Sheet

Rev. G | Page 14 of 20

The output noise spectral density can be calculated by

[

]

2

2

2

2

2

2

2

4

4

1

4

F

G

F

S

G

F

R

ien

kTRg

R

R

ven

R

ien

kTRs

R

R

kTRf

en

vout

+













+

+

+













+

+

=

_

(6)

where:

k is Boltzmann’s Constant.

T is the absolute temperature, degrees Kelvin.

ien is the amplifier input current noise spectral density, pA/√Hz.

ven is the amplifier input voltage spectral density, nV/√Hz.

Figure 40.

Source resistance noise, amplifier voltage noise (ven), and the

2.1 nV/√Hz input voltage noise and 1.4 pA/√Hz input current,

the noise contributions of the amplifier are relatively small for

source resistances between approximately 200 Ω and 30 kΩ.

Figure 41 shows the total RTI noise due to the amplifier vs. the

source resistance. In addition, the value of the feedback resistors

used impacts the noise. It is recommended to keep the value of

feedback resistors between 250 Ω and 1 kΩ to keep the total

noise low.

1000

0.1

10

100k

SOURCE RESISTANCE (

Ω)

100

10

1

100

1k

10k

TOTAL AMPLIFIER NOISE

SOURCE RESISTANCE NOISE

AMPLIFIER + RESISTOR NOISE

Figure 41. RTI Noise vs. Source Resistance

HEADROOM CONSIDERATIONS

The ADA4841-1/ADA4841-2 are designed to provide maximum

input and output signal ranges with 16-bit to 18-bit dc linearity.

As the input or output headroom limits are reached, the signal

linearity degrades.

The input stage positive limit is almost exactly a volt below the

positive supply at room temperature. Input voltages above that

start to show clipping behavior. The positive input voltage limit

increases with temperature with a coefficient of about 2 mV/°C.

The lower supply limit is nominally below the minus supply;

therefore, in a standard gain configuration, the output stage

limits the signal headroom on the negative supply side. Figure 42

and Figure 43 show the nominal CMRR behavior at the limits of

the input headroom for three temperatures—this is generated

using the subtractor topology shown in Figure 44, which avoids

the output stage limitation.

300

–300

3.00

5.00

COMMON-MODE VOLTAGE (V)

260

220

180

140

100

60

20

–20

–60

–100

–140

–180

–220

–260

3.20

3.40

3.60

3.80

4.00

4.20

4.40

4.60

4.80

–40°C

+25°C

+125°C

0

–800

–6.00

–4.00

COMMON-MODE VOLTAGE (V)

–50

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

–650

–700

–750

–5.80 –5.60 –5.40 –5.20 –5.00 –4.80 –4.60 –4.40 –4.20

–40°C

+25°C

+125°C

Figure 44. Common-Range Subtractor