GD80960JF-33 datasheet(16/78 Pages) INTEL

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80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

3.1

Pin Descriptions

This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)

package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid

Array (MPBGA).

Section 3.1.1, “Functional Pin Definitions”, describes pin function; Section 3.1.2, “80960Jx

132-Lead PGA Pinout”, Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” and Section 3.1.4,

“80960Jx 196-Ball MPBGA Pinout”, define the signal and pin locations for the supported package

types.

3.1.1

Functional Pin Definitions

Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with

the bus interface are described in Table 3. Pins associated with basic control and test functions are

described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.

Table 2.

Pin Description Nomenclature

Symbol

Description

Input pin only.

Output pin only.

I/O

Pin can be either an input or output.

–

Pin must be connected as described.

Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.

S(E) Edge sensitive input

S(L) Level sensitive input

A (...)

Asynchronous. Inputs may be asynchronous relative to CLKIN.

A(E) Edge sensitive input

A(L) Level sensitive input

R (...)

While the processor’s RESET pin is asserted, the pin:

R(1) is driven to VCC

R(0) is driven to VSS

R(Q) is a valid output

R(X) is driven to unknown state

R(H) is pulled up to VCC

H (...)

While the processor is in the hold state, the pin:

H(1) is driven to VCC

H(0) is driven to VSS

H(Q) Maintains previous state or continues to be a valid output

H(Z) Floats

P (...)

While the processor is halted, the pin:

P(1) is driven to VCC

P(0) is driven to VSS

P(Q) Maintains previous state or continues to be a valid output

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