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GD80960JF-33 数据表(PDF) 41 Page - Intel Corporation |
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GD80960JF-33 数据表(HTML) 41 Page - Intel Corporation |
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41 / 78 page  Advance Information Datasheet 41 80960JA/JF/JD/JT 3.3 V Microprocessor 4.5 VCCPLL Pin Requirements To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node connecting VCCPLL must be as short as possible. Figure 9. VCCPLL Lowpass Filter 100 VCC (Board Plane) VCCPLL (On 80960Jx) Ω (80960JA/JF/JD) F_CA078A 0.01 µF 4.7 µF + 10 Ω (80960JT) |
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