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THS1040CPWR 数据表(PDF) 22 Page - Texas Instruments |
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THS1040CPWR 数据表(HTML) 22 Page - Texas Instruments |
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22 / 32 page ![]() THS1040 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 22 www.ti.com PRINCIPLES OF OPERATION operating configuration examples (continued) Figure 30 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input with 1.5-Vp-p span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap reference output at VREF to 0.75 V. Tying MODE to AVDD then sets the REFT and REFB voltages via the internal reference generator for a 1.5-Vp-p ADC input range. If a transformer is used to generate the differential ADC input from a single-ended signal, then the BIASREF pin provides a suitable bias voltage for the secondary windings center tap when MODE = AVDD. AIN+ AIN− VREF = 0.75 V REFB MODE REFSENSE AVDD 1.875 V 1.125 V 1.875 V 1.125 V 1.5 V 1.5 V REFT 5 k Ω 10 k Ω 0.1 µF 10 µF 20 pF 20 pF 20 Ω 20 Ω 0.1 µF 0.1 µF 10 µF Figure 30. Operating Configuration: 1.5-V Differential Input, Internal ADC References Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing a dc-coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for the AIN− pin and also, via a buffered potential divider, the 0.75 VREF voltage required to set the input range to 1.5 Vp-p MODE is tied to AVDD to set internal ADC references configuration. AIN+ AIN− REFT MODE REFB 2 V 0.5 V 1.25 V VREF AVDD 10 k Ω _ + REFSENSE AVDD 15 k Ω (0.75 V) 1.25 Source 0.1 µF 10 µF 0.1 µF 0.1 µF 20 pF 20 pF 20 Ω 20 Ω 10 µF Figure 31. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source |
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