ADE9000ACPZ datasheet(59/73 Pages) AD

59 / 73 page

ADE9000

Data Sheet

Rev. A | Page 58 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

PAGE_FULL

Set this bit to enable an interrupt when a page

enabled in the WFB_PG_IRQEN register is filled.

0x0

R/W

WFB_TRIG_IRQ

Set this bit to enable an interrupt when This bit

is set when the waveform buffer has stopped filling

after an event configured in WFB_TRIG_CFG occurs.

0x0

R/W

DREADY

Set this bit to enable an interrupt when new

waveform samples are ready. The update rate

depends on the data selected in the WF_SRC bits in

the WFB_CFG register.

0x0

R/W

CF4

Set this bit to enable an interrupt when the CF4

pulse is issued, when the CF4 pin goes from a

high to low state.

0x0

R/W

CF3

Set this bit to enable an interrupt when the CF3

pulse is issued, when the CF3 pin goes from a

high to low state.

0x0

R/W

CF2

Set this bit to enable an interrupt when the CF2

pulse is issued, when the CF2 pin goes from a

high to low state.

0x0

R/W

CF1

Set this bit to enable an interrupt when the CF1

pulse is issued, when the CF1 pin goes from a

high to low state.

0x0

R/W

REVPSUM4

Set this bit to enable an interrupt when the CF4

polarity changed sign.

0x0

R/W

REVPSUM3

Set this bit to enable an interrupt when the CF3

polarity changed sign.

0x0

R/W

REVPSUM2

Set this bit to enable an interrupt when the CF2

polarity changed sign.

0x0

R/W

REVPSUM1

Set this bit to enable an interrupt when the CF1

polarity changed sign.

0x0

R/W

REVRPC