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ADE9000ACPZ 数据表(PDF) 64 Page - Analog Devices |
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ADE9000ACPZ 数据表(HTML) 64 Page - Analog Devices |
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64 / 73 page  Data Sheet ADE9000 Rev. A | Page 63 of 72 Addr. Name Bits Bit Name Settings Description Reset Access 0x424 ADC_REDIRECT [31:21] RESERVED Reserved. 0x0 R [20:18] VC_DIN VC channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 000 IA ADC data. 001 IB ADC data. 010 IC ADC data. 011 IN ADC data. 100 VA ADC data. 101 VB ADC data. 110 VC ADC data. 111 VC ADC data. [17:15] VB_DIN VB channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 VB ADC data. [14:12] VA_DIN VA channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 VA ADC data. [11:9] IN_DIN IN channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 IN ADC data. [8:6] IC_DIN IC channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 IC ADC data. [5:3] IB_DIN IB channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 IB ADC data. [2:0] IA_DIN IA channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 0x7 R/W 111 IA ADC data. 0x425 CF_LCFG [31:23] RESERVED Reserved. 0x0 R 22 CF4_LT If this bit is set, the CF4 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, then the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. 0x0 R/W 21 CF3_LT If this bit is set, the CF3 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. 0x0 R/W 20 CF2_LT If this bit is set, the CF2 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. 0x0 R/W 19 CF1_LT If this bit is set, the CF1 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. 0x0 R/W [18:0] CF_LTMR If the CFx_LT bit in the CF_LCFG register is set, this value determines the active low pulse width of the CFx pulse. 0x0 R/W |
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