AD6676 datasheet(83/90 Pages) AD

83 / 90 page

Data Sheet

AD6676

Rev. D | Page 83 of 90

Interface Control 1 Register

Address: 0x1E4, Reset: 0x00, Name: SYNC_PIN

Table 109. Bit Descriptions for SYNC_PIN

Bits

Bit Name

Description

Reset

Access

[7:6]

RESERVED

0x0

SYNC_PIN_INV

0 = do not invert SYNCINB pin; SYNCINB is active low.

0x0

1 = invert SYNCINB pin; SYNCINB is active high.

[4:2]

RESERVED

0x0

INV_10B

0 = do not invert octets.

0x0

1 = invert all bits in 10-bit octets from framer. Setting the bit to 1 has the same effect

as swapping the differential output data pins.

RESERVED

0x0

Interface Test Register

Address: 0x1E5, Reset: 0x00, Name: TEST_GEN

Table 110. Bit Descriptions for TEST_GEN

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

RESERVED

0x0

[5:4]

TEST_GEN_SEL

Test Point.

0x0

Insert test data at framer input (16 bits).

Insert test data at PHY input (10 bits).

Insert test data at scrambler input (8 bits).

[3:0]

TEST_GEN_MODE

Test Mode.

0x0

0000

Normal mode; test disabled.

0001

Alternating checkerboard.

0010

1/0 word toggle.

0011

Long PN sequence.

0100

Short PN sequence.

0101

Repeating user pattern mode.

0110

Single user pattern mode.

0111

Ramp. Note that in single lane mode the Q sample is 1 LSB less than the

I sample. In other words, Q[n] = I[n] – 1 LSB, where n is nth IQ sample.

1000

Modified RPAT sequence.

1001

Not used.

1010

JSPAT sequence.

1011

JTSPAT sequence.

ILAS Count Register

Address: 0x1E6, Reset: 0x00, Name: KF_ILAS

Table 111. Bit Descriptions for KF_ILAS

Bits

Bit Name

Description

Reset

Access

[7:0]

KF_ILAS

Initial Lane Assignment Sequence Count. The ILAS is transmitted (KF_ILAS + 1) times.

0x00

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