AD9993BBCZ datasheet(19/57 Pages) AD

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AD9993

Data Sheet

Rev. A | Page 18 of 56

Figure 23. Differential Double Balun Input Configuration

In the double balun and transformer configurations, the value of

the input capacitors and resistors is dependent on the input

frequency and source impedance. Based on these parameters,

the value of the input resistors and capacitors may need to be

adjusted or some components may need to be removed. Table 7

displays recommended values to set the RC network for the

0 MHz to 100 MHz frequency range:

Table 7. Example RC Network

Component

Value

R1 Series

33 Ω

C1 Differential

8.2 pF

R2 Series

0 Ω

C2 Shunt

15 pF

R3 Shunt

49.9 Ω

The values given in Table 7 are for each R1, R2, C1, C2, and R3

component shown in Figure 22 and Figure 23.

ADRF6518 as ADC Driver

The ADRF6518 is a variable gain amplifier and low-pass filter

that is designed to drive the analog inputs of analog-to-digital

converters like the ones included in the AD9993. A principle

application of the ADRF6518 is as part of the signal chain in a

wideband radio receiver. Figure 32 shows a block diagram for a

wideband microwave radio that includes the ADRF6518 and

the AD9993.

The low impedance (<10 Ω) output buffers of the ADRF6518

are designed to drive ADC inputs. They are capable of delivering

up to 4 V p-p composite two-tone signals into 400 Ω differential

loads with >60 dBc IMD3. The output common-mode voltage

can be adjusted to 900 mV (the AD9993 input common-mode

voltage) without loss of drive capability by presenting the

ADRF6518 VOCM pin with the desired common-mode voltage.

The high input impedance of VOCM allows the AD9993 refer-

ence output (A_CML, B_CML, C_CML or D_CML) to be

connected directly.

DACs

The MxFE DACs are part of the Analog Devices high speed

CMOS DAC core family. These DACs are designed to be used

as part of wide bandwidth communication system transmitter

signal chains.

DAC TRANSFER FUNCTION

The AD9993 DACs provide two differential current outputs:

IOUTA_P/IOUTA_N, and IOUTB_P/IOUTB_N.

The DAC output current equations are as follows:

IOUTx_P = IOUTFS × DACx input code/214

IOUTx_N = IOUTFS × ((214 − 1) − DACx input code)/214

where:

DACx input code = 0 to 214 − 1.

IOUTFS is the full-scale output current or DAC gain specified in

Table 1.

IOUTFS = 32 × IIREFx

where IREFx = VREFDAC/RFSADJ_x.

Each DAC has its own IREFx set resistor, RFSADJ_x. RFSADJ_x resistors

can be on or off chip at the discretion of the users. The nominal

value of RFSADJ_x is 1.6 kΩ. The nominal value of VREFDAC is 1.0 V.

VREFDAC can be selected as the on-chip band gap reference or as

an external user supplied reference.

DAC outputs have a sin(πfOUT/fDAC)/(πfOUT/fDAC) envelope

response as a function frequency. This response is also referred

to as a sinc envelope.

DAC OUTPUT COMPLIANCE VOLTAGE RANGE

AND AC PERFORMANCE

Each DAC has a pair of differential current outputs. The

compliance voltage range for each of these two outputs is

specified in Table 1. Optimal DAC ac performance is achieved

when the output common-mode voltage is between 0.0 V and

0.5 V. and the signal swing falls within the compliance range.

x_VINP

x_VINN x_CML

ADC

0.1µF

2V p-p

0.1µF

33Ω

0.1µF

33Ω

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