AD9993BBCZ datasheet(21/57 Pages) AD

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AD9993

Data Sheet

Rev. A | Page 20 of 56

CLOCKING

The clock signals for the LVDS lanes, the DACs, and the ADCs

are developed from a single master clock signal. This signal is

either input directly on the CLKP/CLKN pins or synthesized by

an on-chip PLL multiplier using the REFCLK input signal as a

reference. The ADC output and DAC input LVDS lanes run at

the master clock frequency divided by 2 and are DDR. Data is

clocked on both edges. The sampling rate of the ADCs is ¼ the

master clock rate. The sampling rate of the DACs is ½ the

master clock frequency. A 1 GHz master clock is shown in

Figure 1.

At a 1 GHz master clock frequency, the other on-chip clock

frequencies are as follows:



DCO (ADC DDR LVDS output lane clock): 500 MHz



DCI (DAC DDR LVDS input lane clock): 500 MHz



DAC sampling rate: 500 MSPS



ADC sampling rate: 250 MSPS

ON-CHIP PLL CLOCK MULTIPLIER

Figure 25 shows a block diagram of the MxFE on-chip PLL

clock multiplier. If the PLL clock multiplier is used to generate

the master clock, the buffered VCO output signal is divided by 4

to produce the synthesized master clock signal.

The reference clock of the on-chip PLL can be either 31.25 MHz

or 62.5 MHz. When using a 62.5 MHz clock, a divide by 2

option is provided, as shown in Figure 25, such that the internal

PLL reference clock can be set to 31.25 MHz.

A programmable loop filter is integrated on chip. At reset, the

on-chip loop filter bandwidth is set to 500 kHz. Lower loop

bandwidth can be achieved using an external loop filter

connected to the CP pin, as shown in Figure 25.

An on-chip LDO provides the supply voltage for the VCO.

PLL Synthesizer Control and Status Registers

At reset, the SYNTH_INT register contains the reset default

value for the VCO output divider of 64 (shown in Figure 25).

The PLL multiplier lock status can be read back on Bit 1 of the

SYNTH_STAT register. Calibration status is also read from this

charge pump calibration and to start synthesizer calibration.

Synthesizer calibration is required as part of the process of

acquiring lock. Charge pump calibration and synthesizer

calibration are steps described in the Power-Up Routine When

Using the On-Chip Clock Synthesizer section.

Figure 25. On-Chip PLL Clock Multiplier Block Diagram

VCO

CAL

PFD

DIVIDER

÷64

BUF

VCO

LDO

VDD = 1.8V

VCO

4GHz

BYP_R3

NOTES

1. WHEN USING EXTERNAL LOOP FILTER SET C1, C2, C3, R1, AND R3 TO

MIN OR MAX VALUES AS DEFINED IN REGISTER DESCRIPTION, AS DESIRED.

EXT_CP

_SEL

REFCLK =

31.25MHz

1.5V

FIXED

PROGRAMABLE

REG 0x031

ON-CHIP LOOP FILTER

PROGRAMABLE BY

REG 0x02E TO REG 0x030

C62

390pF

C67

22nF

R110

487Ω

DIVIDER

÷2

BUF

0.1µF

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