AD7607

Data Sheet

Rev. C | Page 12 of 32

Pin No.

Type1

Mnemonic

Description

9, 10

DI

CONVST A,

CONVST B

Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to

initiate conversions on the analog input channels. For simultaneous sampling of all 8 input channels

CONVST A and CONVST B can be shorted together and a single convert start signal applied.

Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4; and

CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7,

and V8). This is possible only when oversampling is not switched on.

When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold

circuitry for their respective analog inputs is set to hold.

11

DI

RESET

Reset Input. When set to logic high, the rising edge of RESET resets the AD7607. The part should

receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a

RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied

during a read, the contents of the output registers reset to all zeros.

12

DI

RD/SCLK

Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/Serial Clock Input When

the Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the

output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers.

MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the

13

DI

CS

Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic

low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on

the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock

out the MSB of the serial output data.

14

DO

BUSY

Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges

and indicates that the conversion process has started. The BUSY output remains high until the

conversion process for all channels is complete. The falling edge of BUSY signals that the

conversion data is being latched into the output data registers and is available to read after a

occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high.

15

DO

FRSTDATA

Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back

on the parallel, parallel byte, or serial interface. When the CS input is high, the FRSTDATA output

pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode,

the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, which

indicates that the result from V1 is available on the output data bus. The FRSTDATA output returns

to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling

edge after the CS falling edge. See the Conversion Control section for more details.

22 to 16

DO

DB[6:0]

Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state

parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0

of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND. When

operating in parallel byte interface mode, DB[7:0] outputs the 14-bit conversion result in two RD

operations. DB7 is the MSB, and DB0 is the LSB.

23

P

Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the

operating voltage of the interface. This pin is nominally at the same supply as the supply of the host

interface (that is, DSP and FPGA).

24

DO

this pins acts as a three-state parallel digital input/ output pin. When CS and RD are low, this pin is

used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as

When operating in parallel byte mode, DB7 is the MSB of the byte.

25

DO

this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is

used to output DB8 of the conversion result. When PAR/ SER/BYTE SEL = 1, this pin functions

31 to 27

DO

DB[13:9]

Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state

parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to

DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND.