Data Sheet

AD7607

Rev. C | Page 13 of 32

Pin No.

Mnemonic

Description

32

DO/DI

DB14/HBEN

Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/SER/BYTE SEL = 0, this pin

acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output

DB14 of the conversion result, which is a sign extended bit of the MSB, DB13. When PAR/SER/BYTE

SEL = 1 and DB15/BYTE SEL = 1, the AD7607 operates in parallel byte interface mode, in which the

HBEN pin is used to select if the most significant byte (MSB) or the least significant byte (LSB) of the

conversion result is output first. When HBEN = 1, the MSB byte is output first, followed by the LSB

byte. When HBEN = 0, the LSB byte is output first, followed by the MSB byte.

33

DO/DI

DB15/

BYTE SEL

Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PAR/SER/BYTE SEL =

0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to

output DB15, which is a sign extended bit of the MSB, DB13, of the conversion result. When PAR/

SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode or parallel byte

interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7607

operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7607

operates in parallel byte interface mode.

34

DI

REF SELECT

Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal

reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and

an external reference voltage must be applied to the REFIN/REFOUT pin.

36, 39

P

REGCAP

Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be

decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of

2.5 V to 2.7 V.

42

REF

REFIN/

REFOUT

Reference Input (REFIN)/Reference Output (REFOUT). The gained up on-chip reference of 2.5 V

is available on this pin for external use if the REF SELECT pin is set to a logic high. Alternatively, the

internal reference can be disabled by setting the REF SELECT pin to a logic low, and an external

reference of 2.5 V can be applied to this input (see the Internal/External Reference section).

Decoupling is required on this pin for both the internal or external reference options. A 10 µF

capacitor should be applied from this pin to ground close to the REFGND pins.

43, 46

REF

REFGND

Reference Ground Pins. These pins should be connected to AGND.

44, 45

REF

REFCAPA,

REFCAPB

Reference Buffer Output Force/Sense Pins. These pins must be connected together and

decoupled to AGND using a low ESR 10 μF ceramic capacitor.

49, 51, 53,

55, 57, 59,

61, 63

AI

V1 to V8

Analog Inputs. These pins are single-ended analog inputs. The analog input range of these

channels is determined by the RANGE pin.

50, 52, 54,

56, 58, 60,

62, 64

AI GND

V1GND to

V8GND

Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 to Analog Input Pin V8.

All analog input AGND pins should connect to the AGND plane of a system.

1

P = power supply, DI = digital input, DO = digital output, REF = reference input/output, AI = analog input, GND = ground.