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AD7983BCPZ-R2 数据表(PDF) 22 Page - Analog Devices |
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AD7983BCPZ-R2 数据表(HTML) 22 Page - Analog Devices |
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22 / 25 page ![]() Data Sheet AD7983 Rev. B | Page 21 of 24 CHAIN MODE WITHOUT BUSY INDICATOR This mode can be used to daisy-chain multiple AD7983s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7983s is shown in Figure 34, and the corresponding timing is given in Figure 35. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7983 enters the acquisition phase and goes into standby mode. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7983s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate can be reduced due to the total readback time. DIGITAL HOST CONVERT CLK DATA IN AD7983 SDO SDI CNV A SCK AD7983 SDO SDI CNV B SCK Figure 34. Chain Mode Without Busy Indicator Connection Diagram tCONV tCYC tSSDISCK tSCKL tSCK tHSDISCK tACQ ACQUISITION tSSCKCNV ACQUISITION tSCKH CONVERSION SDOA = SDIB tHSCKCNV SCK CNV SDIA = 0 SDOB tEN DA15 DA14 DA13 DB15 DB14 DB13 DB1DB0DA15 DA14 DA0 DA1 DA1DA0 tHSDO 12 3 15 16 17 14 18 30 31 32 tDSDO Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing |
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