93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749D-page 4

 2003 Microchip Technology Inc.

FIGURE 1-1:

SYNCHRONOUS DATA TIMING

TABLE 1-3:

INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)

TABLE 1-4:

INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

ERASE

1

11

A5A4A3A2

A1

A0

—

(RDY/BSY)9

ERAL

1

00

1

0

X

X

X

X

—

(RDY/BSY)9

EWDS

1

00

0

0

X

X

X

X

—

HIGH-Z

9

EWEN

1

00

1

1

X

X

X

X

—

HIGH-Z

9

READ

1

10

A5A4A3A2

A1

A0

—

D15 - D0

25

WRITE

1

01

A5A4A3A2

A1

A0

D15 - D0

(RDY/BSY)25

WRAL

1

00

0

1

X

X

X

X

D15 - D0

(RDY/BSY)25

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

ERASE

1

11

A6A5A4

A3A2A1A0

—

(RDY/BSY)10

ERAL

1

00

1

0

X

X

XXX

—

(RDY/BSY)10

EWDS

1

00

0

0

X

X

XXX

—

HIGH-Z

10

EWEN

1

00

1

1

X

X

XXX

—

HIGH-Z

10

READ

1

10

A6A5A4

A3A2A1A0

—

D7 - D0

18

WRITE

1

01

A6A5A4

A3A2A1A0

D7 - D0

(RDY/BSY)18

WRAL

1

00

0

1

X

X

X

X

X

D7 - D0

(RDY/BSY)18

CS

CLK

DI

DO

(READ)

DO

(PROGRAM)

STATUS VALID

Note: